Senior Cache Coherency Architect

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $152,000–$241,500 / yr
Employment: Full-time
Posted: 167 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $219k

This role $197k

$137k most similar roles pay here $290k

This role pays less than 61% of similar roles. Most pay $186,975–$250,812 — the shaded band above. At the midpoint, this role pays about $197k versus about $219k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Senior Cache Coherency Architect

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As a Senior Cache Coherency Architect, you will join the team developing scalable, low-latency, and high-bandwidth coherent interconnect systems for products like Grace-CPU-Superchip and Vera-Rubin. You will be responsible for defining consistent interconnect architectures, cache-coherency protocols, and high-performance on-chip interconnect interfaces while ensuring compliance with power, performance, and area requirements. Your daily work involves contributing to IP block specifications, building functional and performance models for NoC fabrics, and collaborating with cross-functional teams across the project lifecycle to support silicon bring-up and post-silicon debug. You will utilize skills in C, C++, Python, and Verilog while applying deep knowledge of AXI, ACE, and CHI protocols. This role focuses on solving complex architectural challenges within memory subsystems and SoC designs to ensure seamless integration across diverse computing platforms including automotive and AI systems.

Skills

Cache Coherency AXI ACE CHI NoC Verilog C C++ Python Simulation Emulation SoC Design VIPs BFMs Silicon Debug

What you'll do

Define consistent interconnect architectures, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
Author specifications for interconnect IP blocks to ensure compliance with cache-coherency standards.
Integrate interconnect IP into the Network-on-Chip (NoC) fabric during the design process.
Develop and maintain functional and performance models for NoC fabrics and IP units.
Ensure interconnect architectures meet specific power, performance, and area (PPA) requirements.
Partner with verification teams to ensure hardware implementations align with architectural specifications.
Support silicon bring-up and post-silicon debug activities as needed.

What we're looking for

Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in processor design or other high-performance semiconductor designs.
Deep understanding of cache coherency and hands-on experience with industry-standard protocols like AXI, ACE, and CHI.
Experience authoring specifications and designing cache-coherent interconnects.
Strong understanding of system and memory subsystem architecture with a focus on cache-coherent interconnect.
Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
Proficiency in C, C++, Python, and Verilog.

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