Senior Performance Modeling Architect, CPU Fabric and LLC

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $152,000–$241,500 / yr
Employment: Full-time
Posted: 151 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $220k

This role $197k

$137k most similar roles pay here $293k

This role pays less than 68% of similar roles. Most pay $190,000–$250,000 — the shaded band above. At the midpoint, this role pays about $197k versus about $220k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Senior Performance Modeling Architect, CPU Fabric and LLC

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As a Senior Performance Modeling Architect, CPU Fabric and LLC, you will join the architecture team to lead the architectural definition and improvement of next-generation CPU cache hierarchies and interconnects. You will develop and maintain high-fidelity, cycle-accurate performance models for coherent interconnects and large-scale shared caches while analyzing bottlenecks across automotive SoCs and multi-mesh data center architectures. Your daily work involves evaluating coherency protocols like CHI and ACE, running industry-standard benchmarks such as SPEC and MLPerf, and collaborating with verification and software teams to optimize hardware topologies. You will utilize C++, SystemC, and Python to build models and automate simulation sweeps. The role requires expertise in CPU microarchitecture, memory consistency models, Network-on-Chip topologies, credit-based flow control, arbitration logic, and advanced memory systems like CXL or HBM to solve complex data movement challenges.

Skills

C++ SystemC Python CPU Microarchitecture Cache Coherency Protocols CHI ACE SPEC MLPerf Network-on-Chip (NoC) ISO 26262 CXL HBM Formal Verification

What you'll do

Develop and maintain cycle-accurate performance models for coherent interconnects and large-scale shared caches using C++ or SystemC.
Analyze performance bottlenecks across automotive SoCs and multi-mesh data center architectures.
Evaluate the performance impact of different coherency protocols and snooping filters on system architecture.
Run and analyze industry-standard benchmarks like SPEC and MLPerf to drive architectural trade-offs.
Correlate performance models with actual silicon results in collaboration with build and verification teams.
Work with software teams to optimize drivers for the underlying hardware topology.
Create internal tools and frameworks to accelerate architectural exploration and data analysis.

What we're looking for

Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience) with a focus on architecture.
5+ years of experience in computer architecture.
Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
Proven experience in C++ or SystemC for cycle-accurate or functional modeling.
Proficiency in Python or similar scripting languages for data processing, visualization, and automation.
Understanding of Network-on-Chip (NoC) topologies, credit-based flow control, and arbitration logic.
Experience managing ISO 26262 requirements alongside data center PPA limitations (preferred).
Experience with PMU events, formal methods, custom tooling, or advanced memory technologies like CXL/HBM (preferred).

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