This role pays more than
80%
of similar roles. Most pay
$164,250–$217,500
— the shaded band above.
At the midpoint, this role pays about
$229k
versus about
$191k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
2218 open roles
on FindRole.
Listed pay typically runs
$175,000–$278,800
across 1816 roles with salary data.
As a Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will develop analog and digital PLL solutions for wireless SoCs intended for mass production. Your daily responsibilities include designing building blocks such as VCOs, DCOs, MMDs, PFDs, filters, TDCs, and LOGEN components. You will perform feasibility studies, trade-off analyses, and oversee layout, floor planning, and verification to ensure successful tape-outs. The role requires deep expertise in analog, mixed-signal, and RF circuit design, including LNAs, PAs, mixers, and baseband filters. You will utilize tools such as Cadence Virtuoso, Spectre RF, Matlab, EMX, HFSS, SystemVerilog, AMS, Nanotime, and Primetime. This position addresses the technical challenge of designing high-performance wireless transceivers in deep sub-micron RFCMOS technology while managing co-existence scenarios and ensuring silicon measurement correlation for volume production.
Design and develop analog and digital PLL building blocks including VCO, DCO, MMD, PFD, and filters.
Develop top-level designs for both PLLs and LOGEN components.
Perform feasibility studies and trade-off analyses to define circuit requirements from system specifications.
Execute transistor-level design and verification starting from initial concept and architecture.
Manage layout, floor planning, and verification processes to ensure successful tape-out.
Collaborate with test engineers to debug, optimize, and correlate silicon measurements against designs.
Address co-existence scenarios and technical requirements for high-performance wireless systems.
What we're looking for
Bachelor's degree and 10+ years of relevant industry experience.
Experience in design and development of Analog and Digital PLLs and LOGEN for high performance applications.
Hands-on experience designing building blocks including TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs, and PFD/CP.
Deep understanding of analog, mixed-signal, and RF circuit design concepts like LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods.
Proficiency in Cadence Virtuoso, Spectre RF, Matlab, and EM simulation tools such as EMX or HFSS.
Familiarity with mixed-signal mode verification methodology using SystemVerilog and AMS.
Extensive experience in PLL and LOGEN silicon characterization and debug.
Ph.D. degree (preferred); experience in noise/spur cancellation, transceiver architectures, timing analysis tools, and deep sub-micron RFCMOS production (preferred).