This role pays more than
87%
of similar roles. Most pay
$164,250–$217,500
— the shaded band above.
At the midpoint, this role pays about
$242k
versus about
$191k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
2218 open roles
on FindRole.
Listed pay typically runs
$175,000–$278,800
across 1816 roles with salary data.
As a Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will develop analog and digital PLL solutions for wireless SoCs to support high-performance wireless connectivity products. Your daily responsibilities include designing building blocks such as VCOs, DCOs, MMDs, PFDs, filters, TDCs, and LOGEN components from concept through transistor-level design and verification. You will collaborate with cross-functional teams to define radio features, perform feasibility studies, manage floor planning, and oversee tape-out processes. The role requires expertise in analog, mixed-signal, and RF circuit design, including LNAs, PAs, and mixers. Required tools and technologies include Cadence Virtuoso, Spectre RF, Matlab, EM simulation tools like EMX or HFSS, and mixed-signal verification methodologies using SystemVerilog and AMS. You will also perform silicon characterization to ensure compliance with specifications for volume production.
Design and develop analog and digital PLL building blocks including VCO, DCO, MMD, PFD, and filters.
Develop analog and digital PLL top levels and LOGEN building blocks for wireless SoCs.
Perform feasibility studies and trade-off analyses to define radio features and system requirements.
Execute the full design cycle from initial concept and architecture to transistor-level design and verification.
Manage layout, floor planning, and verification processes to ensure successful tape-out.
Collaborate with test engineers to debug, optimize, and correlate silicon measurements against specifications.
Address co-existence scenarios and design requirements for high-performance wireless connectivity products.
What we're looking for
BS degree and 10+ years of relevant industry experience.
Experience in design and development of Analog and Digital PLLs and LOGEN for high performance applications.
Hands-on experience designing building blocks including TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs, and PFD/CP.
Deep understanding of analog, mixed-signal, and RF circuit design concepts like LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods.
Proficiency in Cadence Virtuoso, Spectre RF, Matlab, and EM simulation tools such as EMX or HFSS.
Familiarity with mixed-signal mode verification methodology using SystemVerilog and AMS.
Extensive experience in PLL and LOGEN silicon characterization and debug.
Ph.D. degree (preferred); experience in noise/spur cancellation, RF transceiver architectures, timing analysis tools, and deep sub-micron RFCMOS production (preferred).