RFIC Layout Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $200k

$141k most similar roles pay here $241k

This listing doesn't post a salary. Most similar roles pay $168,425–$231,300.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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TL;DR · RFIC Layout Engineer

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The RFIC Layout Engineer joins the wireless SOC organization to develop high-performance, energy-efficient silicon designs. This role involves performing detailed transistor-level layout for various RF and analog circuit blocks, including LNAs, mixers, PLLs, modulators, power amplifiers, and baseband filters. The engineer is responsible for block-level and top-level floorplanning, as well as full verification flows involving extraction, DRC, LVS, and DFM checking. Key tasks include managing layout reviews for power routing, electromigration, signal path checks, and differential matching. Candidates must possess expertise in deep sub-micron CMOS technologies like FinFET, along with proficiency in CADENCE tools and optional scripting in PERL or SKILL. The work focuses on solving complex technical challenges within wireless systems to improve hardware performance through sophisticated layout techniques for device matching, RF shielding, and high-frequency routing.

Skills

RF Layout FinFET Cadence Calibre DRC LVS ERC DFM Perl SKILL CMOS Floorplanning Electromigration RC Delay High-Frequency Routing

What you'll do

Perform detailed transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
Execute block-level and top-level floorplanning in coordination with circuit designers.
Conduct layout reviews for power/ground routing, electromigration, signal path checks, and differential matching.
Perform full verification flows including extraction, DRC, LVS, and DFM checking.
Manage top-level layout integration and project schedules.
Implement advanced layout techniques to minimize parasitics, provide RF shielding, and optimize high-frequency routing.
Identify failure-prone circuit structures and collaborate with designers to resolve potential issues.
Lead other layout engineers during the top-level integration process.

What we're looking for

Minimum of 8 years of related experience required.
Good understanding of RC delay, electromigration, and coupling.
Ability to identify failure-prone circuit/layout structures and collaborate with designers to resolve issues.
Excellent communication skills and ability to work with multi-functional teams.
Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing (preferred).
Experience in custom RF/analog layout for radio transceivers using deep sub-micron CMOS including FinFET (preferred).
Understanding of guard rings, DNW, PN junctions, and sophisticated process effects like LOD and WPE (preferred).
Proficiency in CALIBRE DRC/ERC/LVS in FinFET technology and CADENCE tools; scripting in PERL or SKILL (preferred).