This role pays more than
91%
of similar roles. Most pay
$174,600–$231,000
— the shaded band above.
At the midpoint, this role pays about
$280k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
896 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 876 roles with salary data.
Principal Solutions Architect – Semiconductor Test serves as a senior individual contributor within the manufacturing and product engineering teams to define and lead the technical strategy for semiconductor test operations. This role involves overseeing wafer probe through final package test, modernizing infrastructure, improving yield, and integrating data-driven intelligence across the lifecycle. Key responsibilities include making architectural trade-off decisions on coverage and cost, establishing guidelines for modularity across Advantest and Teradyne platforms, and serving as a liaison for DFT architecture decisions like scan, BIST, JTAG, and boundary scan. The position requires expertise in Python, Perl, C++, and analytics tools like JMP or Spotfire to drive AI/ML techniques for yield learning. The role addresses the technical challenges of testing complex device portfolios, including mixed-signal, RF, high-speed I/O, and advanced packaging technologies like 2.5D/3D and chiplets.
What does a Solutions Architect earn in California?
Median $235750 from 45 postings across 8 companies.
Define the technical strategy and architectural vision for wafer and package test operations.
Lead trade-off decisions regarding test coverage, cost of test, and quality escapes across the full flow.
Establish architectural guidelines for test program modularity and reuse across multiple ATE platforms.
Serve as the primary liaison between build and test engineering for DFT architecture decisions.
Influence SoC and IP builds to ensure optimal testability, observability, and debuggability.
Drive the adoption of AI/ML techniques for yield learning, outlier detection, and test time optimization.
Define and maintain test roadmaps aligned with device technology and manufacturing scale targets.
Mentor senior engineers and establish technical standards across the global test organization.
What we're looking for
15+ years of hands-on semiconductor test engineering experience in a fab, IDM, or OSAT environment.
Extensive knowledge in at least three areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
Experience leading ATE platforms such as Advantest V93000, Teradyn UltraFLEX/ETS, or similar systems.
Strong background in DFT architectures including scan compression, MBIST, LBIST, JTAG, and related methodologies.
Proficiency in test-related scripting and automation using Python, Perl, C++, or platform-native languages.
Experience with mixed-signal, RF, or high-speed I/O testing is highly valued.
Ability to lead multi-site technical initiatives and influence cross-functional teams without direct authority.
MSEE, MSCE, MSCS, or a Ph.D. in a related field (or equivalent experience).
Python
Bash
Test Automation
post silicon validation
Diagnostic Software
Manufacturing Test
Test Fixtures
Test Strategies
Scripting
Data Center
GPU
Electrical Engineering
Computer Engineering