below marketmost similar roles pay hereabove market
This role pays more than
86%
of similar roles. Most pay
$158,850–$235,750
— the blue band above.
At the midpoint, this role pays about
$280k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
The Principal Solutions Architect – Semiconductor Test is a senior individual contributor role within the manufacturing and product engineering teams. This position leads the technical strategy for semiconductor test, covering wafer and package test operations from start to finish. The architect defines test development strategies, leads architectural trade-off decisions on test coverage and cost, and establishes guidelines for modularity across ATE platforms like Advantest and Teradyne. Key responsibilities include driving AI/ML techniques for yield learning, managing DFT architectures such as scan, BIST, and JTAG, and influencing SoC build reviews. Required skills include 15+ years of experience in semiconductor test engineering, proficiency in Python, Perl, or C++, and knowledge of STDF, ATDF, and JMP. The role solves complex problems in yield analysis and test time optimization.
What does a Solutions Architect earn in California?
Median $235750 from 57 postings across 11 companies.
Define the comprehensive test development strategy for wafer-level and package-level testing across all product families.
Lead architectural trade-off decisions regarding test coverage, test time, cost, and quality escapes.
Establish architectural guidelines for test program modularity, reuse, and structure across various ATE platforms.
Serve as the senior liaison for DFT architecture decisions including scan, BIST, JTAG, and embedded compression.
Influence SoC and IP build reviews to ensure device testability, observability, and debug-ability.
Drive the adoption of AI/ML techniques for yield learning, outlier detection, and test time optimization.
Define and maintain test roadmaps aligned with device technology and manufacturing scale targets.
Engage with ATE vendors and industry consortia to influence emerging standards and technology directions.
What we're looking for
15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
Extensive knowledge in at least three areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
Strong background in DFT architectures including scan compression, MBIST, LBIST, JTAG, and related methodologies.
Proficiency in test-related scripting and automation using Python, Perl, C++, or platform-native languages.
MSEE, MSCE, MSCS, or related field degree or equivalent experience.
Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test (preferred).
Ph.D. or equivalent experience in a related field (preferred).
Advantest V93000
Teradyne UltraFLEXplus
Python
C++
Perl
SmarTEST 8
IG-XL
VCD
EVCD
STIL
ATE
IC Failure Analysis
EMMI
OBIRCH
Signal Integrity
Yield Analysis
Digital Vector Processing