below marketmost similar roles pay hereabove market
This role pays more than
94%
of similar roles. Most pay
$138,362–$197,500
— the blue band above.
At the midpoint, this role pays about
$240k
versus about
$168k
for comparable roles.
Based on 240 similar postings.
Employer
About SpaceX
SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.
SpaceX currently has
793 open roles
on FindRole.
Listed pay typically runs
$130,000–$165,000
across 554 roles with salary data.
Principal Signal Integrity Engineer, Satellites (Starlink) joins the Payload Engineering team to provide signal integrity ownership throughout the hardware life-cycle for the Starlink satellite constellation. This role involves managing the intersection of electrical, mechanical, thermal, software, and RF engineering to ensure high-speed connectivity. Key responsibilities include IP evaluation during silicon architecture, package performance evaluation, stack-up material selection, and PCB layout oversight. You will specify, simulate, and troubleshoot wireline and electro-optical communication systems using 10 to 112+ Gbps SERDES, DSPs, and high-bandwidth memory interfaces like DDR4 and LPDDR5. Required skills include proficiency in 3D EM simulation tools such as CST, HFSS, or ADS, along with knowledge of Python and C/C++. You will solve complex hardware challenges involving novel channels, power delivery strategies, and EMI/EMC de-sense problems.
Specify, design, simulate, and verify signal integrity for advanced satellite hardware and high-speed SERDES systems.
Design and optimize transition structures for entire channels from die bump to die bump.
Derive top-level specifications for PCB materials and channel subcomponents.
Root cause and fix issues found in PCB manufacturing, PCBA testing, or satellite integration.
Define simulation workflows, test methodologies, and signoff criteria for all signal integrity needs.
Perform IP evaluation during the silicon architecture stage and evaluate package performance.
Oversee PCB layout and characterize stack-up materials for high-speed digital designs.
What we're looking for
Bachelor’s degree in electrical engineering, computer engineering, or physics.
5+ years of industry experience designing circuits, electronic products, or hardware.
5+ years of experience using 3D EM simulation tools and high-speed digital channel simulators like CST, HFSS, or ADS.
5+ years of research or industry experience with high-speed digital design.
Master’s degree or PhD in electrical engineering or computer engineering with emphasis in electromagnetic theory, transmission line theory, or wireline transceivers (preferred).
5+ years of experience designing hardware from concept through production with a focus on full life-cycle development (preferred).
5+ years of experience architecting, implementing, and debugging cutting-edge DSP based SERDES products (preferred).
5+ years of experience specifying, analyzing, debugging, and working with high-speed, high-bandwidth memory interfaces (preferred).
U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible to obtain required authorizations from the U.S. Department of State.
Signal Integrity
SERDES
DDR4
LPDDR5
GPDDR6
QSPI NOR
eMMC
CST
HFSS
ADS
Python
C
C++
PCB Layout
EMI/EMC
DSP
Wireline Transceivers
High-Speed Digital Design
3D EM Simulation
Signal Integrity
SERDES
DDR4
LPDDR5
GPDDR6
QSPI NOR
eMMC
Python
C
C++
CST
HFSS
ADS
PCB Layout
EMI/EMC
DSP
Wireline Transceivers
High-Speed Digital Design
3D EM Simulation
PCB Layout
Schematic Capture
FPGA
Python
C/C++
Ethernet
DDR4
I2C
SPI
RF Engineering
Power Electronics
Hardware Bring-up
Digital to Analog Converters
High-Speed Digital Communications
SerDes
Space Lasers
Avionics