Principal Memory Controller RTL Design Engineer | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$142,800–$274,800 / yr
Posted
2 days ago
Closes
Dec 15, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 62% of similar roles. Most pay $171,875–$223,700 — the shaded band above. At the midpoint, this role pays about $209k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1633 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 1454 roles with salary data.

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TL;DR · Principal Memory Controller RTL Design Engineer | Microsoft Careers

The Principal Memory Controller RTL Design Engineer will join the Compute Silicon & Manufacturing Engineering team to lead the design and implementation of high-performance DDR4 or DDR5 memory controllers. This role involves defining micro-architectural specifications in Verilog or System Verilog, optimizing for area, power, and performance, integrating functional IP into SoC, and conducting thorough design quality checks including Lint, CDC/RDC, Low Power Intent, and timing QoR. The engineer will also automate tasks using scripting languages like Perl, Tcl, and Python to enhance efficiency. Collaboration with cross-functional teams, IP providers, and adherence to professional integrity are key aspects of the role. Ideal candidates have extensive experience in digital design principles, low power design, high-speed design, and knowledge of front-end tools such as Verilog simulators, connectivity tools, and synthesis and STA tools.

What you'll do

  • Define and implement micro-architectural specification in Verilog or System Verilog.
  • Refine implementation for area, power, and performance optimization.
  • Integrate functional IP into SoC for seamless operation.
  • Write basic tests to exercise functionality of the memory controller block.
  • Perform design quality checks including Lint, CDC/RDC, Low Power Intent, timing QoR.
  • Automate tasks using scripting languages like Perl, Tcl, Python for efficiency.

What we're looking for

  • 10+ years designing and implementing high-performance DDR4 or DDR5 memory controllers.
  • Proficient in Verilog/System Verilog coding for area, power, and performance optimization.
  • Strong understanding of digital design principles and SoC/IP development processes.
  • Expertise in low-power design principles and front-end tools like simulators and checkers.
  • Experience with synthesis and static timing analysis (STA) tools.
  • Scripting skills using Perl, Tcl, Python for automation tasks.
  • Knowledge of industry-standard interface protocols such as CHI, APB, AMBA.

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