Principal Design Engineer

Microsoft

Quick summary

Work type: On-site
Location: —
Salary: $142,800–$274,800 / yr
Posted: 38 days ago
Closes: Nov 16, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $209k

$127k most similar roles pay here $291k

This role pays more than 66% of similar roles. Most pay $165,000–$222,000 — the shaded band above. At the midpoint, this role pays about $209k versus about $194k for comparable roles.

Based on 239 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 571 roles with salary data.

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View all roles at Microsoft

At a glance

TL;DR · Principal Design Engineer

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The Principal Design Engineer role within the Microsoft AISoC Silicon team involves leading high-performance, high-bandwidth system-on-chip (SoC) projects, focusing on IP microarchitecture specification and RTL design in Verilog/SystemVerilog. This position requires expertise in synthesis, timing constraints, power-performance-area trade-offs, and post-silicon debug, with a strong emphasis on collaboration across architecture, verification, and physical design teams to ensure successful SoC integration. Ideal candidates have over 10 years of digital design experience, including complex control logic and network-on-chip designs, as well as die-to-die IP design and CPU or graphics core development, complemented by proficiency in script development for automation and efficiency.

Skills

Verilog SystemVerilog RTL Clock Domain Crossing (CDC) Lint Synthesis Timing constraints Power Performance Area (PPA) Post-Silicon Debug Fabric On Chip Network On Chip Networking ASICs Complex Control Logic Die to die IP design CPU core design Graphics core design Algorithmic designs for AI Script development

What you'll do

Develop and specify microarchitecture for high-performance, high-bandwidth IPs.
Perform RTL design and synthesis using Verilog/SystemVerilog.
Ensure IP integration across various subsystems in SoC.
Optimize designs for Power, Performance, Area (PPA) trade-offs.
Conduct post-silicon debug to resolve implementation issues.

What we're looking for

10+ years of expertise in digital design, including microarchitecture specification and RTL coding.
8+ years of experience delivering successful IP or ASIC/SOC designs.
5+ years of experience in synthesis, timing constraints, and PPA trade-offs.
Experience designing Fabric/Network On Chip, Networking ASICs, or complex control logic.
Proficiency in die-to-die IP design and post-silicon debug.

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