Power Feature Enablement Systems Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$133,200–$199,800 / yr
Posted
18 days ago
Freshness
Confirmed live today
Closes
Sep 9, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k
This role $166k
$123k most similar roles pay here $230k

This role pays less than 69% of similar roles. Most pay $152,200–$214,500 — the shaded band above. At the midpoint, this role pays about $166k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 409 open roles on FindRole.

Listed pay typically runs $164,080–$246,120 across 409 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Power Feature Enablement Systems Engineer

The Power Feature Enablement Systems Engineer serves as a cross-functional technical leader managing power feature workstreams from pre-silicon definition through program end of life. This role involves ensuring the seamless enablement of power management features, including C-state and P-state algorithms, IP dynamic power management, firmware active power management algorithms, and thermal compensation. The engineer will lead teams to achieve performance per watt goals by developing strategies for testing, feature enablement, debugging, and defect resolution. Key responsibilities include collaborating with power architects to define objectives, identifying risks, and providing feedback to architecture, SoC, and firmware teams. Candidates must possess expertise in system-level power management trade-offs across hardware, firmware, and software levels, along with experience in PC architecture, root cause analysis for power issues, and data collection hygiene for CPU, GPU, Memory, and NPU components.

What you'll do

  • Manage power feature workstreams from pre-silicon definition through program end of life.
  • Ensure seamless enablement of power management features across design, silicon validation, firmware integration, and system deployment.
  • Lead teams to achieve performance-per-watt goals by developing strategies for testing, debugging, and defect resolution.
  • Define and integrate specific power management features like C-state/P-state algorithms and thermal compensation.
  • Drive cross-functional technical teams in the triage and resolution of complex power management issues.
  • Identify project risks and develop mitigation plans to ensure product goals are met.
  • Provide continuous improvement feedback to architecture, firmware, and silicon enablement teams.

What we're looking for

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Systems Engineering, or a relevant discipline.
  • Experience ensuring seamless enablement of power management features from design through silicon validation and firmware integration.
  • Ability to lead cross-functional teams in the triage, debug, and resolution of power management feature issues.
  • Experience defining and integrating features such as C-state/P-state algorithms, IP dynamic power management, and thermal compensation.
  • Understanding of system-level power management trade-offs across hardware, firmware, and software levels (preferred).
  • Understanding of system-level thermal, power, frequency, and voltage limited workload behavior (preferred).
  • Knowledge of CPU, GPU, Memory, and NPU power/performance and SW power management (preferred).
  • Strong analytical skills with experience in root cause analysis for power/performance issues (preferred).

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