High Speed IO Validation Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$164,000–$246,000 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday
Closes
Sep 15, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $205k
$134k most similar roles pay here $258k

This role pays more than 57% of similar roles. Most pay $168,500–$231,737 — the shaded band above. At the midpoint, this role pays about $205k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

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At a glance

TL;DR · High Speed IO Validation Engineer

The High Speed IO (HSIO) Validation Engineer joins the team to validate and debug high-speed interfaces across CPU and GPU platforms for data center servers and AI systems. The role involves executing validation plans, performing post-silicon bring-up, characterization, compliance testing, and interoperability validation. You will collaborate with PHY design, firmware, and platform teams to resolve silicon and system-level issues while developing test automation scripts and data analysis tools. Key technical requirements include experience with PCIe Gen5/Gen6/Gen7, UALink, xGMI, CXL, and Ethernet technologies. Candidates must possess a strong understanding of signal integrity, equalization techniques like CTLE and DFE, and proficiency in Python or C/C++. Day-to-day work involves using oscilloscopes, BERTs, VNAs, and protocol analyzers to analyze link training behavior and ensure product quality for high-speed serial interfaces within complex computing environments.

What you'll do

  • Execute validation plans for high-speed IO interfaces including PCIe, UALink, and Ethernet.
  • Perform post-silicon bring-up, characterization, compliance testing, and interoperability validation across multiple platforms.
  • Conduct electrical and protocol-level debugging using oscilloscopes, BERTs, and protocol analyzers.
  • Analyze signal integrity, power integrity, and link training behavior to identify root causes of issues.
  • Develop and enhance test automation scripts and data analysis tools to improve validation efficiency.
  • Investigate and resolve high-speed interface issues in coordination with design, firmware, and board teams.
  • Document validation findings and communicate technical status to project stakeholders.
  • Contribute to the improvement of validation methodologies and lab infrastructure.

What we're looking for

  • Bachelor's, Master's, or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
  • 5+ years of experience in high-speed IO, silicon validation, system validation, or related areas.
  • Experience with high-speed serial interfaces such as PCIe, CXL, Ethernet, UALink, or similar technologies.
  • Strong understanding of signal integrity concepts, channel characteristics, equalization techniques, and link-level behavior.
  • Experience with lab bring-up, validation, and debug using oscilloscopes, BERTs, VNAs, and protocol analyzers.
  • Strong programming and scripting skills in Python, C/C++, or similar languages for automation and data analysis.
  • Experience validating server, AI, networking, or accelerator platforms (preferred).
  • Experience with compliance testing, interoperability testing, or developing automated validation frameworks (preferred).

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