Mixed Signal Digital Design Lead

What you'll do

• Own the architectural definition, RTL implementation, and system-level integration of digital logic for clocking IPs.
• Design complex digital control loops, state machines for adaptive calibration, and DVFS controllers.
• Translate analog specifications into robust digital architectures and define boundaries at the analog-digital interface.
• Drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
• Co-optimize floorplanning with Physical Design Teams to protect sensitive analog nodes from digital switching noise.
• Enforce a rigorous full-chip CDC and RDC sign-off methodology for the clocking network.
• Write robust, synthesizable SystemVerilog RTL for advanced technology nodes like N5 and N3P.

What we're looking for

• 8+ years of professional digital ASIC design experience.
• Deep expertise in writing robust, synthesizable SystemVerilog RTL.
• Direct experience with advanced technology nodes, specifically N5, N3P, and beyond.
• Proven history of steering cross-functional execution from initial concept through successful tapeouts.
• Experience designing digital control loops, state machines for adaptive calibration, DVFS controllers, and fractional-N delta-sigma modulators.
• Ability to translate analog specifications into digital architectures and define analog-digital interface boundaries.
• Knowledge of full-chip CDC and RDC sign-off methodologies for clocking networks.
• Bachelors degree.