Memory Control Design Engineer

Qualcomm

Actively hiring Posted this week Verified listing
San Diego, CA Posted 2 days ago Apply by Nov 29, 2026 $98,500–$147,700 / year
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Salary context

Below market

How this pay compares to similar roles

Similar $184k
This role $123k
$84k most similar roles pay here $233k

This role pays less than 90% of similar roles. Most pay $153,087–$214,093 — the shaded band above. At the midpoint, this role pays about $123k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 615 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 556 roles with salary data.

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At a glance

TL;DR

The ASIC Design Engineer role at Qualcomm Technologies, Inc.'s Memory Controller Design Team involves working on the next generation high-speed DDR Controllers, focusing on the front-end interface with CPUs, DSPs, and multimedia processors. The candidate will be responsible for enabling high-speed (1GHz+) designs in QCT products by developing design specifications and micro-architectures, implementing RTL code, and collaborating closely with verification engineers to ensure high-quality deliverables. Key tasks include synthesis, timing closure, physical design support, gate-level simulations, power analysis, and C/C++ modeling of memory controller IP. The ideal candidate has experience with DDR controller architectures, x86 or ARM CPU/bus architectures, and a background in ASIC design methodologies to enhance productivity and quality results.

Skills

C C++ RTL Verilog VHDL Synthesis Timing_Closure Physical_Design Gate_Level_Simulation Power_Analysis DDR_Controller_Architecture x86_Architecture ARM_Architecture

What you'll do

  • Develop architecture and micro-architecture for high-speed DDR controllers.
  • Implement RTL code and collaborate with verification engineers on design quality.
  • Debug designs and provide support during integration into the chip system.
  • Perform synthesis, timing closure, physical design support, and gate-level simulations.
  • Contribute to C/C++ modeling of memory controller IP.
  • Enhance design methodology to improve productivity and quality results.

What we're looking for

  • Experience in designing high-speed DDR controller architectures.
  • Proficiency in x86 or ARM CPU/bus architectures.
  • Expertise in RTL implementation and verification for memory controllers.
  • Knowledge of synthesis, timing closure, and physical design support.
  • Skills in C/C++ modeling and debugging memory controller IP.
  • Ability to contribute to the improvement of design methodologies.

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