Graphics Design Verification Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
15 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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Similar $203k
$139k most similar roles pay here $259k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Graphics Design Verification Engineer

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As a Graphics Design Verification Engineer within the Silicon Technologies group, you will perform pre-silicon RTL verification of blocks in low power embedded graphics cores. You will lead top-level verification teams for logic blocks in GPU designs while owning the development, execution, and tracking of test plans. Your daily responsibilities include architecting test bench methodologies using System Verilog and UVM, building testing stimulus, managing coverage and regression strategies, and debugging simulation and silicon failures. The role requires a strong background in computer architecture, specifically regarding CPU or GPU architectures. You will utilize tools such as IES, VCS, DVE, and Verdi, alongside Perl, Shell scripting, Makefiles, and TCL. This position focuses on the technical challenge of ensuring high-performance, power-efficient system-on-chip designs function correctly within complex micro-architectural environments to support seamless device performance.

Skills

System Verilog UVM OVM Verilog HDL GPU Architecture RTL Verification Constrained Random Verification Assertion Methodology Code Coverage VCS IES DVE Verdi Perl Shell Scripting Makefiles TCL

What you'll do

  • Lead top-level verification teams for logic blocks within graphics processing unit (GPU) designs.
  • Own the development, execution, and tracking of team test plans.
  • Architect test bench methodologies using SystemVerilog and Universal Verification Methodology (UVM).
  • Develop testing stimulus, coverage strategies, and regression plans.
  • Maintain test benches and Bus Functional Models (BFMs).
  • Debug complex simulation and silicon GPU failures.
  • Coordinate verification efforts with design, micro-architecture, and multi-functional teams.
  • Report weekly status updates to the GPU leadership team.

What we're looking for

  • Bachelor of Science degree and 10 years of relevant experience.
  • Background in CPU or GPU architectures (expertise in GPU architectures preferred).
  • Experience working with Verilog or other HDLs.
  • Experience architecting test benches using SystemVerilog and UVM/OVM.
  • Experience with constrained random verification, functional and code coverage, and assertion methodology.
  • Experience debugging complex design and environmental issues.
  • Experience with various HDL simulators and waveform viewers like IES, VCS, DVE, or Verdi (preferred).
  • Proficiency in Perl, Shell scripting, Makefiles, and TCL (preferred).

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