Gate-level Noise (Signal Integrity) / STA CAD Engineer

What you'll do

• Apply sign-off methodologies and noise margins for gate-level glitch noise and static timing analysis.
• Run and maintain production CAD flows and scripts for core noise and STA tools.
• Execute glitch noise analysis tasks including checking glitch thresholds and propagation reports.
• Perform root-cause analysis of crosstalk glitch and timing anomalies using automated triage workflows.
• Execute noise and timing ECO tasks to support design convergence toward tapeout.
• Participate in tool and version qualification activities to track QoR and performance data.
• Support design and physical design teams with noise and timing constraints and flow issues.

What we're looking for

• BS in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 1-2 years of experience in CAD methodology, EDA support, or digital design (preferred).
• Foundational understanding of gate-level signal integrity, crosstalk glitch noise, and static timing analysis (STA) (preferred).
• Exposure to industry-standard SI and STA tools like PrimeTime-SI or Tempus (preferred).
• Basic scripting skills in Python, Tcl, and/or Perl (preferred).
• Coursework or project exposure to standard cell library noise characterization or SPICE simulation basics (preferred).
• Familiarity with place-and-route concepts and physical design flow basics (preferred).
• Curiosity about AI/LLM-assisted workflows for CAD scripting and automated triage (preferred).