Gate-level Noise (Signal Integrity) / STA CAD Engineer

What you'll do

• Define and architect consistent noise and STA analysis methodologies, margins, and tool qualification strategies.
• Own and drive end-to-end flows and scripts for gate-level noise and static timing analysis tools.
• Conduct deep root-cause analysis of noise violations and timing-path anomalies using LLM-agent pipelines.
• Develop and support noise and timing ECO methodologies and custom scripts for project tapeouts.
• Build infrastructure for large-scale noise/timing report mining, QoR extraction, and visualization.
• Use AI coding agents to prototype and harden new analysis methodologies and waiver-justification logic.
• Create documentation and specifications to serve as grounding context for internal AI assistants.
• Mentor junior engineers on noise/STA analysis techniques and best practices.

What we're looking for

• BS in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 10+ years of industry experience.
• Hands-on experience with signal integrity analysis tools like Tempus, PrimeTime-SI, or ETS/Celtic (preferred).
• Solid understanding of STA fundamentals and PrimeTime specifics, including Tcl coding and reports (preferred).
• Strong Perl, Tcl, and/or Python scripting skills with a systematic debugging approach (preferred).
• Working knowledge of crosstalk, OCV effects, margins, constraints, and aggressor selection (preferred).
• Ability to plan and execute systematic tool and methodology evaluations (preferred).
• Expertise in AI/ML-driven and agentic-workflow innovation for CAD and noise/timing flows (preferred).