Gate-level Noise (Signal Integrity) / STA CAD Engineer

What you'll do

• Develop and maintain production CAD flows and scripts for gate-level glitch noise and static timing analysis.
• Contribute to the development of sign-off methodologies, noise margins, and tool qualification strategies for advanced nodes.
• Support glitch noise analysis including threshold determination, propagation, and impact on functional integrity.
• Perform root-cause analysis of crosstalk glitches and timing anomalies using automated triage workflows and AI-agent pipelines.
• Execute noise and timing ECO methodologies to accelerate design convergence toward tapeout.
• Participate in systematic tool qualifications by tracking QoR, performance, and correlation against golden baselines.
• Author technical documentation and guidelines to share noise and STA best practices with the team.

What we're looking for

• BS in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 3+ years of industry experience.
• Background in gate-level signal integrity, specifically crosstalk glitch noise and static timing analysis (STA) (preferred).
• Hands-on experience with industry-standard SI and STA tools such as PrimeTime-SI or Tempus (preferred).
• Exposure to noise and timing sign-off on advanced process nodes (preferred).
• Experience with noise and timing ECO flows and techniques for design closure (preferred).
• Scripting and automation skills in Python, Tcl, and/or Perl (preferred).
• Familiarity with standard cell library noise characterization or correlating gate-level models with SPICE simulations (preferred).