Emulation Front-End Infrastructure Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 78 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k

This role $177k

$124k $246k

below market most similar roles pay here above market

This role pays less than 51% of similar roles. Most pay $164,875–$214,125 — the blue band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Emulation Front-End Infrastructure Engineer

Role Posting Log in to save

The Emulation Front-End Infrastructure Engineer joins the Emulation Infrastructure team to own and evolve front-end compilation, synthesis, and flow infrastructure for hardware emulation platforms. The role involves developing, maintaining, and automating robust flows using scripting and industry-leading EDA tools to enable pre-silicon validation of complex designs. Key responsibilities include running and debugging regressions, maintaining RTL design stability, and applying AI techniques to improve flow automation and root-cause analysis. Candidates must possess proficiency in Verilog and SystemVerilog, along with experience in RTL elaboration, logic optimization, and front-end design methodologies. Required technical skills include Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE, plus scripting in Python, Perl, Tcl, and shell. Experience with LSF, Slurm, Perforce, and Git is also required.

Skills

Verilog SystemVerilog Python Perl Tcl Shell Scripting Synopsys Design Compiler ZeBu Compiler Cadence HDL-ICE RTL Elaboration LSF Slurm Perforce Git Makefile Hardware Emulation EDA Tools

What you'll do

Own and evolve front-end compilation, synthesis, and flow infrastructure for hardware emulation platforms.
Develop and automate robust compilation and synthesis flows using scripting and industry-leading EDA tools.
Run, analyze, and debug regular compilation and synthesis regressions to maintain RTL design stability.
Apply AI techniques to improve flow automation, triage compilation failures, and accelerate root-cause analysis.
Evaluate, deploy, and support EDA tools and methodologies for front-end implementation and emulation compilation.
Diagnose complex compilation, elaboration, synthesis, and implementation issues in coordination with design teams and vendors.
Improve flow performance, reliability, scalability, usability, and observability across large-scale hardware development environments.

What we're looking for

A BS degree in Electrical Engineering, Computer Engineering, or a related field with 5+ years of relevant experience.
An MS degree in a related field with 3+ years of relevant experience.
Experience with RTL compilation, synthesis, front-end design implementation, and flow automation.
Working proficiency in Verilog and SystemVerilog to read, debug, and modify RTL for emulation needs.
Strong understanding of RTL elaboration, synthesis, logic optimization, and front-end design methodologies.
Hands-on experience with front-end synthesis and compilation EDA tools including Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.
Strong automation and scripting skills in Python, Perl, Tcl, shell scripting, and Makefile-based flows.
Experience running jobs on distributed compute farms using LSF or Slurm and using revision-control systems like Perforce or Git.

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