EDA Workflow Optimization Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAWestford, MAAustin, TXDurham, NC
Salary
$152,000–$241,500 / yr
Posted
13 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $175k
This role $197k
$114k most similar roles pay here $255k

This role pays more than 65% of similar roles. Most pay $127,887–$222,000 — the shaded band above. At the midpoint, this role pays about $197k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · EDA Workflow Optimization Engineer

As an EDA Workflow Optimization Engineer, you will join a specialized team to partner with engineering teams worldwide in optimizing the full chip design process from inception through production. You will investigate flaws and opportunities within workflows, construct performance metrics for services and infrastructure, and build new systems in an agile, production software environment. Your daily work involves participating in the full life-cycle of tool development, testing, and deployment while improving how workflows utilize compute and storage environments to enhance chip development quality and time to market. The role requires expertise in UNIX systems programming, automation using Python, Shell, or Perl, and experience with C/C++. You will leverage knowledge of ASIC, VLSI, CAD/EDA, and mixed-signal design environments, while utilizing tools like IBM Spectrum LSF or SLURM to manage GPU-based workloads in distributed batch computing environments.

What you'll do

  • Investigate and debug complex, multi-discipline problems within a UNIX engineering environment.
  • Optimize chip design workflows from inception through architecture, verification, layout, and production.
  • Build and maintain scalable, high-performance infrastructure in an agile, production software environment.
  • Develop reliable metrics to measure the performance of internal flows, services, and infrastructure.
  • Manage the full life-cycle of tool development, testing, and deployment for chip engineers.
  • Optimize how design workflows utilize compute and storage environments.
  • Automate processes using Python, Shell, or other scripting languages to improve engineering productivity.
  • Analyze data to drive decisions regarding the quality and time-to-market for next-generation chips.

What we're looking for

  • Bachelor of Science in Computer Science or equivalent experience is required; a Master's degree is preferred.
  • Candidates must have at least 5 years of relevant experience.
  • Experience investigating and debugging complex, multi-discipline problems in a UNIX engineering environment is required.
  • Hands-on experience with EDA tools and ASIC, VLSI, CAD/EDA, or mixed signal design workflow environments is required.
  • Proficiency in UNIX Systems programming and automation using Python and/or Shell is required.
  • Experience with architectural decisions in storage, networking, and compute technologies is required.
  • Ability to apply data analysis principles to influence data-driven decisions is required.
  • Experience with job schedulers like IBM Spectrum LSF or SLURM and GPU-based workloads in batch computing environments is preferred.

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