EDA Workflow Optimization Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAWestford, MAAustin, TXDurham, NC
Salary: $152,000–$241,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k

This role $197k

$117k $255k

below market most similar roles pay here above market

This role pays more than 63% of similar roles. Most pay $130,691–$230,887 — the blue band above. At the midpoint, this role pays about $197k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · EDA Workflow Optimization Engineer

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As an EDA Workflow Optimization Engineer, you will join the EDA Workflow Optimization team to partner with global engineering teams across the full chip design process. You will guide teams to improve or reinvent workflows covering inception, architecture, design, verification, emulation, layout, packaging, and production. Your daily responsibilities include performing investigations to identify flaws, constructing performance metrics, and building new infrastructure in an agile production software environment. You will optimize how workflows utilize compute and storage environments to improve chip development quality and time to market. Required skills include experience in ASIC, VLSI, CAD/EDA, or mixed signal design workflows. You must possess hands-on experience with EDA tools, UNIX systems programming, and automation using Python, Shell, C/C++, and Perl. Knowledge of IBM Spectrum LSF, SLURM, and distributed systems is preferred.

Skills

Python C/C++ UNIX Shell Perl EDA Tools ASIC VLSI CAD IBM Spectrum LSF SLURM Data Analysis Batch Computing Networking Storage Compute

What you'll do

Investigate and debug complex, multi-discipline problems within a UNIX engineering environment.
Guide engineering teams to improve or reinvent workflows across the full chip design process.
Build and deploy new infrastructure in an agile, production software environment.
Optimize how chip development workflows utilize compute and storage environments.
Construct and maintain reliable metrics to measure the performance of flows, services, and infrastructure.
Participate in the full life-cycle of tool development, testing, and deployment.
Enhance scalable, reliable, and high-performance systems to support next-generation chip development.

What we're looking for

BS in Computer Science or equivalent experience; MS (preferred).
5+ years of relevant experience.
Strong experience investigating and debugging complex, multi-discipline problems in a UNIX engineering environment.
Hands-on experience with architectural decisions in storage, networking, and compute technologies.
Experience with ASIC, VLSI, CAD/EDA, or mixed signal design workflow environments.
Hands-on experience with EDA tools.
Experience in UNIX Systems programming and automation using Python and/or Shell.
Experience in applying data analysis principles and influencing data-driven decisions.