Digital Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 4 days ago
Closes: Dec 21, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $169k

This role $144k

$105k most similar roles pay here $214k

This role pays less than 67% of similar roles. Most pay $135,187–$203,200 — the shaded band above. At the midpoint, this role pays about $144k versus about $169k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Digital Design Engineer

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Qualcomm’s high speed parallel interfaces team seeks an ASIC front-end design engineer to join their world-class global team focused on architecting and implementing cutting-edge DDR and die-to-die interfaces for high-speed compute and server applications. The role involves designing RTL and digital IPs that connect SoCs to DRAM devices, ensuring reliable high-speed links in multi-die systems. Daily tasks include collaborating with architecture, verification, timing, and physical design teams to develop control and data-path blocks, requiring expertise in System Verilog, logic synthesis, linting checks, clock domain crossing best practices, low power implementation, and gate-level simulation debug. Ideal candidates have hands-on experience with high-speed parallel interfaces and low-power designs, working effectively in a fast-paced environment across cross-functional teams to support all phases of implementation and silicon bring up.

Skills

SystemVerilog ASIC RTL Digital IP Design Logic Synthesis Linting Checks Clock Domain Crossing Low Power Implementation Gate Level Simulation DFT High Speed Parallel Interfaces Design for Test

What you'll do

Design and develop RTL for digital IPs used in SoC to DRAM device connections.
Implement control and data-path blocks for high-speed compute and server interfaces.
Conduct logic synthesis, linting checks, and clock domain crossing analysis for designs.
Perform low power implementation and sign off for digital IP design using System Verilog.
Debug gate level simulations and ensure reliable high-speed links in multi-die systems.
Collaborate with verification, timing, and physical design engineers on project phases.

What we're looking for

Minimum 4 years of ASIC design or verification work experience.
Bachelor’s degree in Science, Engineering, or related field required.
Expertise in digital IP design using System Verilog and logic synthesis.
Hands-on experience with ASIC front-end implementation tool flows.
Knowledge of low power implementation, sign-off, and gate-level simulation.
Experience with high-speed parallel physical interfaces designs preferred.
Ability to work closely with cross-functional teams in a dynamic environment.

Remote

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