Design Verification Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$114,100–$199,000 / yr
Posted
45 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $176k
This role $157k
$102k most similar roles pay here $231k

This role pays less than 67% of similar roles. Most pay $143,012–$209,037 — the shaded band above. At the midpoint, this role pays about $157k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

Join our dynamic team as a Design Verification Engineer and play a pivotal role in ensuring the flawless production of silicon for critical IP designs. Your responsibilities will encompass all pre-silicon verification phases, from establishing robust DV methodologies to developing comprehensive test plans and verification environments using SystemVerilog and UVM. You’ll create scalable and portable test-benches, write detailed test cases, debug failures, and track coverage metrics to ensure design integrity. Leveraging LLMs for efficient execution is also a key aspect of this role. Ideal candidates possess strong OOP knowledge, experience with verification tools like simulators and waveform viewers, and familiarity with scripting languages such as Python or Perl. This position offers the chance to work on cutting-edge SoC/IP projects at scale, addressing complex business challenges in hardware design verification.

What you'll do

  • Develop detailed test and coverage plans based on micro-architecture.
  • Establish scalable and portable verification methodologies for IP designs.
  • Create comprehensive verification environments including stimulus, checkers, assertions.
  • Debug test failures and close bugs during regression testing phases.
  • Track and report design verification progress using various metrics.

What we're looking for

  • Minimum 3 years of relevant industry experience in hardware design verification
  • Strong knowledge of Object-Oriented Programming, SystemVerilog, and UVM
  • Experience developing scalable and portable test-benches
  • Proven expertise with verification methodologies and tools including simulators and coverage collection
  • Familiarity with LLMs for efficient verification processes
  • Knowledge of power-aware verification methodology (UPF) preferred
  • Scripting language proficiency in Python, Perl, or TCL

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