Design Verification Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Melbourne, FL
Posted
45 days ago

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Salary context

How this pay compares to similar roles

Similar $175k
$126k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $142,450–$208,200.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer at our leading-edge hardware team in Melbourne, Florida, you will play a pivotal role in ensuring the successful tape-out of complex IP designs by developing and implementing robust pre-silicon verification methodologies. Your daily tasks will involve creating comprehensive test plans, building scalable verification environments using SystemVerilog and UVM, and leveraging LLMs to enhance efficiency and quality. You will be responsible for debugging regressions, closing bugs, and tracking coverage metrics to ensure thorough validation of the design. This role requires a strong background in object-oriented programming, experience with simulation tools, and familiarity with power-aware verification methodologies. Ideal candidates should have at least three years of industry experience and a solid understanding of serial and parallel protocols, though formal verification and emulation knowledge are beneficial but not mandatory.

Skills

SystemVerilog UVM Python Perl TCL LLMs PCIe USB DDR UPF Formal Verification Emulation Technologies

What you'll do

  • Develop detailed test and coverage plans based on micro-architecture.
  • Establish scalable and portable verification methodologies for IP designs.
  • Create comprehensive verification environments including stimulus, checkers, assertions.
  • Implement regression testing to debug failures and close bugs efficiently.
  • Track and report design verification progress using various metrics.

What we're looking for

  • BS degree in technical field and at least 3 years of relevant industry experience.
  • Strong knowledge of OOP, SystemVerilog, and UVM for design verification.
  • Experience developing scalable and portable test-benches for complex designs.
  • Proficiency with verification methodologies and tools including simulators and coverage collection.
  • Use of large language models (LLMs) to enhance verification efficiency and quality.
  • Familiarity with power-aware verification methodology such as UPF.

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