Design Verification Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Cary, NC
Posted
45 days ago

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Salary context

How this pay compares to similar roles

Similar $175k
$126k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $142,450–$208,200.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer at Apple in Cary, North Carolina, you will join a dynamic team responsible for ensuring the successful delivery of cutting-edge silicon products. Your primary responsibilities include developing comprehensive test plans and verification methodologies to validate IP designs across all pre-silicon phases. You will create scalable and portable verification environments using SystemVerilog and UVM, develop detailed stimulus and checkers, and track coverage metrics to ensure thorough testing. Additionally, you will leverage large language models (LLMs) to enhance the efficiency of your verification processes. This role requires a strong background in object-oriented programming, experience with simulation tools, and familiarity with power-aware verification methodologies. Ideal candidates possess knowledge of scripting languages like Python or Perl, as well as expertise in serial protocols such as PCIe or USB.

Skills

SystemVerilog UVM Python Perl TCL LLMs OOP Simulators Waveform_viewer Build_and_run_automation Coverage_collection Gate_level_simulations UPF PCIe USB DDR Formal_verification_methodology Emulation_for_verification_technologies

What you'll do

  • Develop detailed test and coverage plans based on micro-architecture.
  • Establish DV methodology suitable for IP designs to ensure scalability.
  • Create verification environment including stimulus, checkers, assertions, trackers.
  • Implement regression testing and debug failures in the design.
  • Track and report progress using various metrics like bugs and coverage.

What we're looking for

  • BS degree in technical field and at least 3 years of relevant industry experience.
  • Strong knowledge of OOP, SystemVerilog, and UVM for design verification.
  • Experience developing scalable and portable test-benches for verification environments.
  • Proven expertise with verification methodologies and tools including simulators and coverage collection.
  • Familiarity with LLMs to enhance verification efficiency and quality.
  • Knowledge of power-aware verification methodology (UPF) is beneficial.

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