Design Verification Engineer

Amazon Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TXIrvine, CASan Diego, CA
Salary: $122,600–$170,000 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $179k

This role $146k

$114k $207k

below market most similar roles pay here above market

This role pays less than 90% of similar roles. Most pay $161,125–$197,750 — the blue band above. At the midpoint, this role pays about $146k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 627 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 621 roles with salary data.

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View all roles at Amazon Inc

At a glance

TL;DR · Design Verification Engineer

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Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. In this role, you will implement a state of the art verification environment for IP, subsystem, and SOC to facilitate testing against reference models. You will develop detailed test plans, write tests, run regressions, and collect coverage matrices. You will also debug system level communication scenarios on pre silicon and post silicon environments. The role requires proficiency in UVM, C, SystemC, DPI-C, and scripting, with potential use of Matlab and AI/LLM tools. You will work on modems, high-speed interfaces, embedded processors, and DSP solutions using latest CMOS generation technologies to solve wireless communication problems.

What does a Design Verification Engineer earn in California?

Median $187850 from 56 postings across 6 companies.

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Skills

UVM SystemC DPI-C C Matlab Formal Verification Digital Verification Scripting Modem Design pre silicon post silicon AI/LLM CMOS DSP Test Plans

What you'll do

Implement a state-of-the-art verification environment for IP, subsystem, and SOC components.
Develop detailed test plans and write tests to facilitate testing against reference models.
Run regressions and collect coverage matrices to report progress to the program.
Debug system-level communication scenarios in both pre-silicon and post-silicon environments.
Participate in system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
Develop a highly automated environment to triage regression fails and report issues to stakeholders.

What we're looking for

Must be a U.S. citizen, national, permanent resident, refugee, or granted asylum.
Bachelor's degree in Electrical Engineering or a related field.
1+ year of experience with UVM, C, SystemC, and scripting.
2+ years of experience in verification, preferably in communication systems.
Master's or Ph.D. degree in Electrical / Communications Engineering (preferred).
2+ years in digital verification, preferably in communication systems (preferred).
Proficiency in leveraging AI/LLM tools to accelerate verification workflows (preferred).
Export control laws and regulations, candidates.

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