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Active Keyword: CPU RTL Remove filter Clear all

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CPU RTL/AI Micro-Architect - AI Development

Qualcomm

Austin, TX 12 days ago $179,000–$268,400
Actively hiring Verified listing Competitive pay
AI Python Verilog SystemVerilog VHDL Kubernetes Docker CI/CD Prometheus Grafana AWS Git Jenkins PostgreSQL SQLite
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CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 23 days ago $167,100–$250,700
Actively hiring Above market
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Questa TCL SV CI/CD
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RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 30 days ago $142,200–$213,400
Actively hiring Competitive pay
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 36 days ago $167,100–$250,700
Actively hiring Above market
Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques
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CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 36 days ago $154,000–$231,000
Actively hiring Competitive pay
RISC-V RTL Verilog SystemC VHDL Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power design Performance optimization Area and timing goals Communication skills Collaboration skills Teamwork skills
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CPU RTL Methodology Engineer

Qualcomm

Santa Clara, CA +1 68 days ago $198,700–$298,100
Actively hiring Above market
Python Git Verilog SystemVerilog TCL Perl Bash CI/CD CAD RTL
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CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm

Austin, TX +1 88 days ago $148,300–$250,700
Actively hiring Competitive pay
Verilog VHDL Perl Python Waveform debugging tools Simulators Instruction fetch and decode Branch prediction Instruction scheduling Register renaming Out-of-order execution Integer execution Floating point execution Load/store execution Prefetching Cache subsystems Memory subsystems Logic design principles Timing analysis Power analysis Low power techniques High performance techniques
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