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Active Keyword: CPU RTL Remove filter Clear all

20 of up to 20 (filtered)

CPU Core RTL Design Engineer

Amd

Austin, TX 6 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction
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CPU RTL Design Engineer

Amd

Austin, TX 21 days ago $121,680–$182,520
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 25 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp
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Director, CPU RTL Design Engineering

Amd

Remote (Santa Clara, CA) 32 days ago $248,800–$373,200
Actively hiring Confirmed live today High trust Above market
RTL Design x86 Computer Architecture Processor Pipeline Memory Hierarchy Instruction Set Architecture Logic Design Python Ruby Perl Silicon Development Lifecycle Tapeout Scripting Automation
Remote
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CPU Microarchitecture & Cache RTL Design Engineer

Amd

Fort Collins, CO 34 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday High trust Below market
VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric
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CPU RTL Methodology Engineer

Qualcomm

Santa Clara, CA +1 34 days ago $209,300–$313,900
Actively hiring Confirmed live yesterday High trust Above market
RTL Design Verilog SystemVerilog Python TCL Perl Bash GIT CI/CD CAD Tools CPU Microarchitecture Hardware Design Automation Frameworks Build Systems
6+ yrs exp
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Next Gen CPU Power Management RTL Design Engineer

Amd

Santa Clara, CA 39 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design
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CPU-Core RTL Director

Qualcomm

Austin, TX +1 39 days ago $228,400–$342,600
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog RTL Design Microarchitecture CPU Design Physical Design DFT CAD Emulation Timing Closure Power Optimization Silicon Debug PPA SIMD MMU Virtualization Automation
8+ yrs exp
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CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 39 days ago $216,600–$325,000
Actively hiring Confirmed live today Low trust Above market
RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
8+ yrs exp
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CPU RTL/AI Micro-Architect

Qualcomm

Austin, TX +1 39 days ago $186,700–$280,100
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog VHDL RTL Design LLM Agentic AI Simulation Waveform Debug Logic Design Synthesis CPU Architecture Microarchitecture Hardware Engineering
6+ yrs exp
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CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Power and Area Tradeoffs
3+ yrs exp
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CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems
10+ yrs exp
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CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging CPU Architecture
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CPU Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog VHDL C C++ Python Perl Microarchitecture Formal Verification Simulation Emulation Out-of-Order Execution Branch Prediction
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
10+ yrs exp
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
3+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Waveform Debugging
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Cache Memory Subsystems Waveform Debugging
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
3+ yrs exp
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