This role pays more than
98%
of similar roles. Most pay
$152,875–$216,250
— the shaded band above.
At the midpoint, this role pays about
$275k
versus about
$185k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
Chipset Power Engineer
The Chipset Power Engineer joins the Data Center team to develop high-performance, energy-efficient server solutions for data center applications. This role focuses on the estimation, analysis, and optimization of power, performance, and thermal metrics for server chipsets at advanced process nodes. The engineer will build end-to-end power modeling frameworks to support specific server use cases, perform tradeoff analyses for various workloads, and identify gaps to meet product KPIs. Key responsibilities include collaborating with cross-functional teams to optimize hardware and software features. Required expertise includes SoC power estimation methodologies, modeling of datacenter workloads, digital ASIC design, and CMOS circuit power fundamentals. The role also involves managing active power, idle low power, silicon limits, and power delivery systems like multi-phase bucks and LDOs while addressing the technical challenges of high-performance server chipsets in hyperscale environments.
Develop end-to-end power modeling frameworks to support specific server use cases.
Perform tradeoff analyses for various workloads and system use cases.
Identify performance gaps relative to targets and propose feature enhancements to meet product KPIs.
Optimize power, performance, and thermal metrics for server chipsets at advanced process nodes.
Model workload data for datacenter SoCs to improve power estimation accuracy.
Coordinate with cross-functional teams to optimize hardware and software for low-power features.
Analyze peak current transients of various IPs within the system.
Evaluate silicon test methodologies to drive power and thermal optimizations.
What we're looking for
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of relevant engineering experience.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of relevant engineering experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant engineering experience.
Over 10 years of experience in power estimation, modeling, and optimization of CPU/SoCs, with at least 5 years in high-performance server chips (preferred).
Master's in Computer Science/Engineering, Electrical Engineering, or related field with 15 years of experience in low power design and optimization (preferred).
Expertise in power management of high-performance systems, digital ASIC design, CMOS circuits, and power delivery systems like multi-phase bucks and LDOs (preferred).
Experience in hardware/software co-design for low power features, silicon test methodologies, and hyperscale data center solutions (preferred).
Strong technical documentation skills and excellent written and verbal communication abilities.
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