Cellular ASIC Design Engineer – Protocols

Apple Inc

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $181,100–$318,400 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $250k

$130k most similar roles pay here $339k

This role pays more than 92% of similar roles. Most pay $168,862–$224,450 — the shaded band above. At the midpoint, this role pays about $250k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer – Protocols

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As a Cellular ASIC Design Engineer at our cutting-edge hardware team, you will play a pivotal role in architecting and implementing protocol processing hardware for next-generation wireless SoCs. Your responsibilities include micro-architecture design and RTL implementation, optimizing pipelining architectures to enhance performance metrics, driving latency optimization, defining HW/FW/SW partitioning, developing architectural prototypes, and bringing up hardware in the lab for validation. You will leverage SystemVerilog, Verilog, synthesis tools, and timing analysis software while applying low-power design techniques and AMBA bus protocols. Expertise in cellular MAC, WiFi MAC, IP/TCP/UDP protocols, network infrastructure architecture, packet buffering, queuing, scheduling, security algorithms, and memory subsystems is highly valued as you tackle complex challenges in a high-scale environment.

Skills

SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols network infrastructure architecture routers access points switches packet buffering queuing security algorithms AES memory subsystems C SystemC

What you'll do

Design micro-architecture and implement RTL for cellular protocol hardware.
Analyze and optimize pipelining architectures to enhance performance metrics.
Drive latency optimization and QoS support for efficient data handling.
Define partitioning strategies between HW/FW/SW for protocol processing.
Develop architectural prototypes to validate design decisions early in the process.
Bring up and debug hardware in laboratory settings for validation.

What we're looking for

Hands-on expertise in SystemVerilog and Verilog.
Skilled in synthesis and timing analysis tools.
Experience with low-power design techniques.
Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip NoCs.
Expertise in designing and optimizing scheduling and QoS mechanisms.

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