Cellular ASIC Design Engineer – Protocols

Apple Inc

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$120,300–$210,100 / yr
Posted
52 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $165k
$107k most similar roles pay here $243k

This role pays less than 77% of similar roles. Most pay $171,125–$224,450 — the shaded band above. At the midpoint, this role pays about $165k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer – Protocols

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As a Cellular ASIC Design Engineer at our cutting-edge hardware team, you will play a pivotal role in architecting and implementing protocol processing hardware for advanced wireless SoCs. Your responsibilities include micro-architecture design and RTL implementation, optimizing pipelining architectures to enhance performance metrics, and driving latency optimization alongside QoS support. You will also define the partitioning of HW/FW/SW components for efficient protocol processing and develop architectural prototypes to validate early-stage decisions. Additionally, you will be involved in bringing up hardware in the lab and debugging issues collaboratively with software, firmware, and verification teams. The ideal candidate should have hands-on experience with SystemVerilog and Verilog, proficiency in AMBA bus protocols like AXI or AHB, and a solid understanding of low-power design techniques and cellular MAC protocols.

Skills

SystemVerilog Verilog Synthesis tools Timing analysis tools Low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms C SystemC AES Packet buffering Queuing Scheduling Memory subsystems仲裁设计

What you'll do

  • Design micro-architecture and implement RTL for cellular protocol hardware.
  • Analyze and optimize pipelining architectures to enhance performance metrics.
  • Drive latency optimization and quality of service (QoS) support.
  • Define partitioning strategies between HW/FW/SW for protocol processing.
  • Develop architectural prototypes to validate design decisions early in the process.
  • Bring up and debug hardware in laboratory settings.

What we're looking for

  • Hands-on experience in SystemVerilog and Verilog.
  • Experience with synthesis and timing analysis tools.
  • Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip NoCs.
  • Understanding of cellular MAC, WiFi MAC, or other data-link layer (L2) protocols.
  • Background in network infrastructure architecture including routers, access points, switches.
  • Experience in designing and optimizing scheduling and QoS mechanisms.

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