Cellular ASIC Design Engineer – Protocols

Apple Inc

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$171,600–$302,200 / yr
Posted
52 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $237k
$132k most similar roles pay here $320k

This role pays more than 80% of similar roles. Most pay $168,862–$224,450 — the shaded band above. At the midpoint, this role pays about $237k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer – Protocols

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As a Cellular ASIC Design Engineer at our cutting-edge hardware team, you will play a pivotal role in architecting and implementing protocol processing hardware for future wireless SoCs. Your responsibilities include micro-architecture design and RTL implementation, optimizing pipelining architectures to enhance performance metrics, driving latency optimization, and defining HW/FW/SW partitioning. You will also develop architectural prototypes, bring up hardware in the lab, and collaborate closely with software and firmware teams to ensure high-quality deliverables. This role requires expertise in SystemVerilog and Verilog, proficiency with synthesis and timing analysis tools, and a solid understanding of AMBA bus protocols like AXI or AHB. Additionally, experience with low-power design techniques and scheduling/QoS mechanisms is essential for success in this challenging yet rewarding position.

Skills

SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols packet buffering queuing scheduling designs security algorithms C SystemC

What you'll do

  • Design micro-architecture and implement RTL for cellular protocol hardware.
  • Analyze and optimize pipelining architectures to enhance performance metrics.
  • Drive latency optimization and QoS support in hardware design.
  • Define partitioning strategies between HW/FW/SW for protocol processing.
  • Develop architectural prototypes to validate early-stage design decisions.
  • Bring up and debug hardware in laboratory settings.

What we're looking for

  • Hands-on expertise in SystemVerilog and Verilog for RTL implementation.
  • Skilled in synthesis and timing analysis tools for hardware optimization.
  • Experience with low-power design techniques to enhance efficiency.
  • Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip networks.
  • Expertise in designing and optimizing scheduling and QoS mechanisms.

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