Cellular ASIC Design Engineer – Protocols

Apple Inc

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $126,800–$220,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k

This role $174k

$114k most similar roles pay here $242k

This role pays less than 69% of similar roles. Most pay $168,862–$224,450 — the shaded band above. At the midpoint, this role pays about $174k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer – Protocols

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As a Cellular ASIC Design Engineer at our cutting-edge hardware team, you will play a pivotal role in architecting and implementing protocol processing hardware for advanced wireless SoCs. Your responsibilities include micro-architecture design and RTL implementation, optimizing pipelining architectures to enhance performance metrics, and driving latency optimization with robust QoS support. You will also define the partitioning of HW/FW/SW components for efficient protocol processing and develop architectural prototypes to validate your designs early in the development cycle. Essential skills include hands-on experience with SystemVerilog and Verilog, synthesis and timing analysis tools, and low-power design techniques. Familiarity with AMBA bus protocols and cellular MAC or WiFi MAC protocols is highly desirable. This role involves close collaboration with software, firmware, and verification teams to ensure hardware that excels in performance, flexibility, and power efficiency for large-scale network infrastructure applications.

Skills

SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols packet buffering queuing scheduling security algorithms AES memory subsystems C SystemC

What you'll do

Design micro-architecture and implement RTL for cellular protocol hardware.
Analyze and optimize pipelining architectures to enhance performance metrics.
Drive latency optimization and QoS support for efficient data handling.
Define partitioning strategies between HW/FW/SW for protocol processing.
Develop architectural prototypes to validate design decisions early in the process.
Bring up and debug hardware in laboratory settings for validation.

What we're looking for

Hands-on experience in SystemVerilog and Verilog.
Experience with synthesis and timing analysis tools.
Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip NoCs.
Understanding of cellular MAC, WiFi MAC, or other data-link layer (L2) protocols.
Background in network infrastructure architecture including routers, access points, switches.
Experience in designing and optimizing scheduling and QoS mechanisms.