Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $181,100–$318,400 / yr
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $250k

$132k most similar roles pay here $338k

This role pays more than 92% of similar roles. Most pay $165,200–$223,700 — the shaded band above. At the midpoint, this role pays about $250k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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The Technical Lead role within the Hardware team requires an experienced professional with a minimum of 10 years in relevant industry experience and a BS degree. This senior position focuses on leading analysis and validation efforts for system-on-chip (SoC) designs, emphasizing power, performance, area, and cost optimizations. Day-to-day responsibilities include rapid prototyping methodologies, scripting test chip block implementations, and leveraging synthesis, place-and-route tools to explore implementation options. Candidates should possess a deep understanding of physical design challenges and be proficient in using industry-standard EDA tools for efficient SoC development. This role is integral to addressing complex business problems related to optimizing hardware designs at scale within the semiconductor industry.

Skills

Python Shell Tcl VHDL Verilog Synopsys Cadence Mentor Graphics PowerPC ARM Linux CI/CD Git JIRA Confluence

What you'll do

Conduct power, performance, area, and cost optimizations for SoCs.
Lead rapid prototyping and scripting of methodologies for test chip blocks.
Implement efficient design solutions to address physical design challenges.
Utilize synthesis, place and route tools for effective implementation exploration.
Explore various implementation strategies to enhance design efficiency.

What we're looking for

Minimum BS degree and at least 10 years of relevant industry experience.
Experience in Power, Performance, Area, and Cost optimizations for SoCs.
Ability to rapidly prototype methodologies and implement test chip blocks.
Strong understanding of Physical Design challenges and proficiency with synthesis tools.
Expertise in place and route tools and implementation exploration techniques.

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