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Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Posted: 67 days ago
Closes: Sep 27, 2026
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $180k

$123k most similar roles pay here $247k

This listing doesn't post a salary. Most similar roles pay $152,037–$208,800.

Based on 238 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 558 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 401 roles with salary data.

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At a glance

TL;DR · Careers

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The ASIC Design Engineer role at Qualcomm Technologies Inc.'s Memory Controller Design Team involves developing high-speed DDR controllers for QCT products, focusing on the front-end interface with CPUs, DSPs, and multimedia processors. The candidate will be responsible for designing and implementing RTL code, collaborating closely with verification engineers to ensure high-quality designs, and conducting synthesis, timing closure, and physical design support tasks. Key responsibilities include debugging designs both independently and in collaboration with other teams during integration phases, as well as contributing to C/C++ modeling of memory controller IP. The ideal candidate has 3-8 years of experience with DDR controller architectures and familiarity with x86 or ARM CPU/bus architectures, aiming to enhance design methodologies for improved productivity and quality results within a large-scale semiconductor environment.

Skills

Verilog SystemC VHDL RTL UVM C C++ DDR LPDDR PCDDR x86 ARM Synopsys Cadence TCL Mentor Graphics Python Git SVN JIRA Confluence

What you'll do

Design and develop high-speed DDR controller interfaces for CPUs, DSPs, and multimedia processors.
Implement RTL code and collaborate with verification engineers to ensure design quality.
Debug memory controller designs and provide support during chip integration.
Conduct synthesis, timing closure, physical design support, and gate-level simulations.
Participate in C/C++ modeling of memory controller IP and contribute to design methodology improvements.

What we're looking for

At least 3-8 years of experience in ASIC design engineering.
Expertise in DDR controller architectures, particularly the front-end interface to CPU/DSP/MMU.
Proficiency with x86 or ARM CPU/bus architectures.
Strong skills in RTL implementation and collaboration with verification engineers.
Experience in synthesis, timing closure, physical design support, gate-level simulations, and power analysis.
Ability to contribute to C/C++ modeling of memory controller IP.
Regular contributions to improving design methodology for productivity and quality.

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