Analog/Mixed Signal Verilog Modeling Design Engineer

What you'll do

• Develop Digital-Mixed Signal (DMS) models of analog IPs using SystemVerilog.
• Support the chip verification team by providing accurate analog/mixed signal models.
• Model complex analog circuits including LDOs, TIAs, muxes, and converters.
• Create testbenches and implement digital RTL components like FSMs and clock dividers.
• Perform SV versus schematic verification for leaf models using Cadence tools.
• Utilize scripting languages such as TCL, Perl, or Python to automate tasks.
• Use AI tools like Cursor and chipAgents to generate analog SV models from specifications.

What we're looking for

• Bachelor's degree in a related field.
• 8+ years of related experience.
• Proficiency in developing Digital-Mixed Signal (DMS) models using SystemVerilog.
• Knowledge of Verilog-AMS modeling language and SystemVerilog UDT/UDR nettypes.
• Familiarity with analog circuits such as LDOs, TIAs, muxing, SARADC, comparators, DACs, and buffering.
• Proficiency in RTL coding for digital design (e.g., clock dividers, decoders, FSM) and testbench creation.
• Experience with Cadence linting and simulation tools (ncsim, xrun, vcs) and analog schematic editors.
• Hands-on skills in scripting languages like TCL, Perl, or Python; experience with AI tools for model generation is preferred.