This role pays more than
99%
of similar roles. Most pay
$168,500–$238,787
— the shaded band above.
At the midpoint, this role pays about
$328k
versus about
$204k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3553 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2740 roles with salary data.
The AMS SerDes Robustness Analysis Validation Architect joins the hardware team to drive robustness, performance, and margin validation of high-speed SerDes PHYs, including PCIe and USB. This role involves architecting validation strategies that go beyond standard spec-checking to uncover design weaknesses through stress-to-fail methodologies across various PVT conditions and real-world environments. The architect will develop techniques for testing equalization paths, clocking structures, jitter sensitivities, and link training edge cases while collaborating with design and system teams to improve design-for-test observability. Key responsibilities include leading hands-on lab experiments, performing root-cause analysis on silicon behaviors, and optimizing test coverage versus execution time. Required skills include expertise in SerDes design, signal integrity, power integrity, and programming in Python or C/C++. The role addresses the technical challenge of ensuring reliable high-speed serial link performance across complex system interactions.
Architect margin-to-fail validation strategies to uncover weaknesses in high-speed SerDes PHYs across various PVT and system environments.
Develop stress-to-fail methodologies for equalization paths, clocking structures, jitter sensitivities, and link training edge cases.
Collaborate with design teams to define coverage priorities and integrate necessary design-for-test (DFT) features or sensors.
Lead hands-on lab experiments to isolate issues, root-cause failures, and validate technical assumptions at the circuit and system levels.
Optimize the validation pipeline by balancing comprehensive test coverage against execution time constraints.
Analyze silicon behavior across multiple builds to provide feedback for future architectural decisions and design updates.
Mentor junior engineers on debug techniques and contribute to internal standard processes for SerDes validation.
What we're looking for
Bachelor of Science degree and 20+ years of relevant industry experience.
PhD in Electrical Engineering or related field with 20+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug (preferred).
Hands-on lab experience with oscilloscopes, BERTs, protocol analyzers, and measurement setups for SerDes PHYs (preferred).
Deep understanding of high-speed serial link protocols and equalization techniques (preferred).
Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity and power integrity impacts (preferred).
Skilled in programming languages like Python or C/C++ and data analysis tools for validation automation (preferred).
Proven ability to root-cause issues at the circuit, protocol, and system levels (preferred).
Experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks (preferred).