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SystemVerilog UVM OVM Python C++ Verilog VHDL SystemC Perl Linux Makefiles Formal Verification Generative AI 3GPP DSP RTL Design +11 more Show less

Signal Integrity FPGA Xilinx Altera HDL SERDES DDR3 DDR4 DDR5 I2C JTAG UART SPI PCIe eMMC Linux Mentor Graphics DxDesigner Vivado Quartus HyperLynx Sigrity PowerSI PowerDC ADS Ansys HFSS SPICE Python Perl +22 more Show less

PCB Design Cadence Allegro Mentor Expedition SPICE PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet JTAG Signal Integrity Power Integrity BMC x86 ARM SMBus PMBus SPI PWM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less

PCB Design Cadence Allegro Mentor Expedition SPICE PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet Signal Integrity Power Integrity JTAG BMC SMBus PMBus SPI PWM x86 ARM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less

PCB Design Cadence Allegro Mentor Expedition Signal Integrity Power Integrity PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet JTAG SPICE x86 ARM BMC SMBus PMBus SPI PWM Oscilloscopes Logic Analyzers Circuit Simulation +16 more Show less