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SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

Python C++ Matlab VPI JMP PAM4 coherent_optical_communications RF_EO_OE_testing client_optics_DSP_SerDes_testing DAC_ADC_operations test_automation data_analysis_software software_and_testAutomation +8 more Show less

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD +9 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

SystemVerilog UVM C++ Python Perl Constrained-random testing Functional coverage Assertions CI/CD Debugging Performance profiling Memory subsystems Coherent interconnects GPU architecture Formal verification Emulation +11 more Show less

SystemVerilog UVM ASIC Linux C C++ Python Perl Networking Formal verification +5 more Show less

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow +6 more Show less