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Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

Electrical Engineering Power Electronics Digital Circuit Design PCB Design Schematic Capture MATLAB Simulink PSpice Mentor Graphics PADS Siemens Xpedition Circuit Card Assembly (CCA) Test Instrumentation Oscilloscopes Multimeters Signal Processing design-for-manufacturability +11 more Show less

SystemVerilog UVM OVM Python C++ Verilog VHDL SystemC Perl Linux Makefiles Formal Verification Generative AI 3GPP DSP RTL Design +11 more Show less

RTL Verilog System Verilog Python C C++ ASIC Low Power Design Synthesis Linux Perl Makefiles XML GenAI Computer Architecture Embedded Systems +11 more Show less

RTL Verilog SystemVerilog C++ SystemC Python Perl Linux DSP 3GPP 4G 5G Low Power Design Synthesis Generative AI Makefiles XML +12 more Show less

Primetime Tempus Innovus Redhawk Python TCL Perl Unix shell SSTA IR analysis Statistical data analysis Data science Revision control Flow automation +9 more Show less

Python PCBA FPGA Signal Integrity High-Speed Interfaces Oscilloscopes Multimeters Power Supplies Sensors RF Microcontrollers System-on-Chip Data Analysis Test Automation Requirements Traceability +10 more Show less

Solidworks NX AutoCAD Python C++ LabVIEW Mechanical Design CAD Motion Systems Vacuum Systems Pneumatics Machine Imaging Sensing Systems AI Data Analysis System Control +11 more Show less