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Hardware Design for Test (DFT) Intern

Nvidia

Santa Clara, CA 5 days ago
Actively hiring Confirmed live today Posted this week Trusted
Design for Test (DFT) Digital Design Static Timing Analysis (STA) ATPG Boundary Scan JTA Memory BIST Logic BIST Streaming Scan Network Perl TCL C C++ Python Synopsys TetraMAX Cadence Modus Linux
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Senior DFT/ATPG Engineer, Mixed-Signal IP

Amd

Fort Collins, CO 24 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
ATPG DFT Scan Design Gate-Level Simulation Fault Simulation Python Perl Tcl SDF Mixed-Signal IP Silicon Bring-up Post-Silicon Debug Failure Analysis waveform-debug
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Principal DFT Engineer

SpaceX

Austin, TX +2 89 days ago
Actively hiring Confirmed live today Low trust
DFT ASIC Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST RTL Verilog SystemVerilog Python Perl Tcl UPF Formal Verification DRC ATE SDF Gate Level Simulation
10+ yrs exp
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Principal DFT Engineer

SpaceX

Irvine, CA +2 89 days ago $210,000–$340,000
Actively hiring Confirmed live yesterday Low trust Above market
DFT ASIC Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST Python Perl Tcl Verilog SystemVerilog RTL UPF Formal Verification DRC ATE SDF Gate Level Simulation
10+ yrs exp
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Principal DFT Engineer

SpaceX

Palo Alto, CA +2 89 days ago $220,000–$355,000
Actively hiring Confirmed live today Low trust Above market
DFT ASIC Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST Python Perl Tcl Verilog SystemVerilog RTL UPF Formal Verification DRC ATE SDF Gate Level Simulation
10+ yrs exp
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