below marketmost similar roles pay hereabove market
This role pays more than
80%
of similar roles. Most pay
$177,250–$241,750
— the blue band above.
At the midpoint, this role pays about
$250k
versus about
$210k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
510 open roles
on FindRole.
Listed pay typically runs
$172,000–$258,000
across 510 roles with salary data.
The Sr DFT/ATPG Engineer–Mixed-Signal IP will own the scan architecture and validation strategy for analog and mixed-signal intellectual property. Working within a cross-functional team, the engineer will define scan architectures, develop ATPG models for custom digital and mixed-signal circuitry, and deliver production-quality test patterns. Key responsibilities include validating scan-stitched gate-level netlists, analyzing test coverage for stuck-at and transition-delay faults, and performing zero-delay and SDF-annotated gate-level simulations. The role requires proficiency with industry-standard ATPG, gate-level simulation, and waveform-debug tools, alongside scripting skills in Python, Perl, or Tcl. This position solves complex engineering challenges by ensuring robust, manufacturable test solutions for complex IP and SoC designs, supporting silicon bring-up, yield learning, and post-silicon failure analysis through technical leadership and collaborative problem-solving.
Define and document scan architectures for analog and mixed-signal IP considering timing, power, and area.
Develop and maintain ATPG models for custom digital, analog-interface, and mixed-signal circuitry.
Validate scan-stitched gate-level netlists including scan-chain connectivity, test-mode controls, and cross-domain behavior.
Analyze and improve test coverage for stuck-at and transition-delay faults to meet targets.
Perform zero-delay and SDF-annotated gate-level simulations to resolve timing issues and netlist mismatches.
Manage the full lifecycle of production test patterns from generation and validation to delivery.
Support silicon bring-up, yield learning, and post-silicon failure analysis with product and test engineering teams.
Identify and resolve testability issues to improve architecture, methodology, and automation.
What we're looking for
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, a closely related technical field, or equivalent practical experience.
Experience with scan design, ATPG, fault simulation, coverage analysis, and pattern validation for complex IP or SoC designs (preferred).
Experience applying DFT methodologies to analog and mixed-signal IP, including modeling custom circuitry and interfaces for ATPG (preferred).
Experience with industry-standard ATPG, gate-level simulation, waveform-debug, and DFT verification tools (preferred).
Knowledge of multiple fault models, such as stuck-at, transition-delay, cell-aware, bridging, or comparable advanced defect-oriented models (preferred).
Experience identifying and resolving scan-chain, netlist, constraint, clocking, reset, timing, and X-propagation issues (preferred).
Knowledge of zero-delay and SDF-annotated simulation flows and production pattern formats (preferred).
Experience supporting silicon bring-up, production test deployment, yield learning, post-silicon failure analysis, or closely related activities (preferred).