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Active Keyword: SR Design Verification Engineer Remove filter Location: Santa Clara Remove filter Clear all

3 of up to 20 (filtered)

Senior Design Verification Engineer

Amd

Santa Clara, CA +1 46 days ago $141,760–$212,640
Actively hiring Confirmed live today High trust Below market
SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification
Hybrid
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Senior Design Verification Engineer

Amd

Santa Clara, CA 117 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
C++ SystemVerilog UVM Python Verilog RTL Design Verification Scripting Perl AI-driven development Testbench Infrastructure Coverage Closure
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Senior Design Verification Engineer

Amd

Santa Clara, CA 140 days ago $141,760–$212,640
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification
Save