Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: GPU Design Verification Engineer Remove filter Location: Santa Clara Remove filter Clear all

6 of up to 20 (filtered)

GPU Physical Verification Design Engineer

Apple Inc

Santa Clara, CA 15 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
Physical Verification DRC ERC LVS Calibre P&R Floorplanning GPU Architecture Tapeout multi Vt ESD Design for Yield
10+ yrs exp
Save

GPU Design Verification Engineer

Apple Inc

Santa Clara, CA 15 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM Verilog VHDL RTL Verification Graphics Pipeline Perl Ruby Shell Scripting Makefiles Simulations Waveform Viewers Functional Coverage SoC Computer Architecture
10+ yrs exp
Save

GPU Design Verification Engineer

Apple Inc

Santa Clara, CA 15 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM Verilog VHDL RTL Verification GPU Architecture Graphics Pipeline Perl Ruby Shell Scripting Makefiles Simulations Waveform Viewers Functional Coverage SoC
3+ yrs exp
Save

GPU Design Verification Engineer

Apple Inc

Santa Clara, CA 15 days ago $129,300–$194,700
Actively hiring Confirmed live today High trust Below market
SystemVerilog Verilog RTL Verification Perl Ruby Shell Scripting Makefiles Computer Architecture GPU Architecture HDL Simulators Waveform Viewers Data Structures Object Oriented Programming SoC
Save

GPU Design Verification Engineer

Qualcomm

San Diego, CA +3 15 days ago $169,500–$254,300
Actively hiring Confirmed live today High trust Competitive pay
System Verilog UVM Verilog VHDL C C++ Python Vulkan FPGA Emulation Palladium Zebu QEMU Make Airflow GDB uboot UEFI
4+ yrs exp
Save

Senior ASIC Design Verification Infrastructure and Tools Engineer

Nvidia

Remote (Santa Clara, CA) +3 50 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics
5+ yrs exp Remote
Save