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Serdes Silicon Design and Micro-Architecture Engineer

Amd

San Jose, CA 5 days ago $232,000–$348,000
Actively hiring Confirmed live today Posted this week High trust Above market
Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Firmware Loops Post-silicon Validation

SerDes Silicon Design and Micro-Architecture Engineer

Amd

San Jose, CA 12 days ago $188,160–$282,240
Actively hiring Confirmed live today High trust Above market
Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Post-silicon Validation Firmware Loops

Principal Micro-architect, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 15 days ago $221,700–$364,800
Actively hiring Confirmed live today High trust Above market
RTL Design Verilog SystemVerilog ASIC Design Flow STA DFT ECO AMBA5 CHI AMBA4 ACE AXI Coherent Interconnect LLC Python Perl Computer Architecture Memory Subsystem Architecture
10+ yrs exp

CPU Micro-architect

Samsung Electronics

San Jose, CA +1 67 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
CPU Microarchitecture C++ Python Verilog Arm ISA x86 RISC-V OoO CPU TLB Branch Prediction SpecInt17 GB6 Hardware Description Languages Root Cause Analysis
4+ yrs exp

Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 67 days ago $151,000–$251,800
Actively hiring Confirmed live today Trusted Competitive pay
Verilog VHDL ASIC Design Flow RTL Design AMBA ACE AXI CHI STA DFT ECO Python Perl Logic Synthesis Timing Analysis Floor-planning Memory Controller Coherent Interconnect Cache Design On-chip Network Topologies
6+ yrs exp