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Active Keyword: Chip Lead Remove filter Location: San Jose Remove filter Clear all

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Senior Chip Lead Engineer SoC/ASIC

Amd

San Jose, CA 8 days ago $164,000–$246,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC FPGA RTL Verilog SystemVerilog VHDL EDA Tools Physical Design Timing Closure Power Optimization DFT Silicon Validation Device Drivers Low-level Software AI/ML Accelerators
10+ yrs exp
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Chip Lead, ASIC Director

Amd

San Jose, CA 106 days ago $248,800–$373,200
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC RTL Physical Design Timing Closure Post-silicon Validation FPGA Tapeout Verification Custom Design Design for Test Floorplan Architecture
Hybrid
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