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Active Keyword: ASIC Design Verification Engineer Remove filter Location: San Jose Remove filter Clear all

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ASIC Design Verification Engineer

Cisco

San Jose, CA 3 days ago $167,700–$245,200
Actively hiring Confirmed live 2 days ago Posted this week High trust Competitive pay
System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug
7+ yrs exp
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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 38 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation
8+ yrs exp
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ASIC Design Verification Engineering Leader

Cisco

Remote (San Jose, CA) 38 days ago $214,100–$309,800
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4
10+ yrs exp Remote
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ASIC Design Verification Engineer

Cisco

Remote (San Jose, CA) 53 days ago $165,000–$241,400
Actively hiring Confirmed live yesterday Low trust Competitive pay
System Verilog UVM ASIC Design C C++ Python Perl Linux Formal Verification Networking Post-silicon Lab Bring-up
7+ yrs exp Remote
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