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Active Keyword: Sr. ASIC Design Engineer Remove filter Location: Irvine Remove filter Clear all

5 of up to 20 (filtered)

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Irvine, CA +3 3 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
RTL Verilog System Verilog ASIC SoC AXI AHB Python EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
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Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Redmond, WA +3 3 days ago $165,000–$270,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
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Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Austin, TX +3 3 days ago
Actively hiring Confirmed live yesterday Posted this week Trusted
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 81 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 130 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
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