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ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 12 days ago
Actively hiring Confirmed live today High trust
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp

Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 105 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting
5+ yrs exp

ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 132 days ago $129,400–$207,000
Actively hiring Confirmed live today High trust Below market
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl OOP SVA Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp