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Active Keyword: Design Verification Engineer Remove filter Location: Broomfield Remove filter Clear all

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ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 12 days ago
Actively hiring Confirmed live yesterday High trust
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp
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Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom

Mendota Heights, MN +1 49 days ago $109,700–$175,500
Actively hiring Confirmed live today High trust Below market
Mixed-Signal Verification UVM SystemVerilog Verilog VHDL SVA Static Timing Analysis Logic Synthesis Place and Route Formal Verification Python Perl TCL CMOS Bipolar EDA Tools
8+ yrs exp
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Design Verification Engineer

Broadcom

Broomfield, CO +4 84 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday High trust Competitive pay
SystemVerilog UVM SVA RTL Gate-level Netlist Python Perl Tcl FPGA Emulation Synopsys Cadence Mentor Git DesignSync Mixed-Signal SDF Co-simulation
10+ yrs exp
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ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 132 days ago $129,400–$207,000
Actively hiring Confirmed live today High trust Below market
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl OOP SVA Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp
Save