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CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 125 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp

CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 148 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp