Browse tech roles

SystemVerilog UVM Python C++ Digital Design SoC Architecture DV Methodology PCIe DDR SPI I2C UART AIML HVL Coverage-Driven Verification Multi-processor Systems Cellular 5G FW-HW Interactions +13 more Show less

SystemVerilog UVM Python C++ Java Digital Design SoC Architecture DDR PCIe SPI I2C UART USB AIML HVL Coverage-Driven Verification FW-HW Interaction Multi-processor Systems Memory Controller +14 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification +14 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification +14 more Show less