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CPU RTL Design Engineer

Amd

Austin, TX 4 days ago $121,680–$182,520
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 9 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp

CPU Core RTL Design Engineer

Amd

Austin, TX 94 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Power Management Post-Silicon Debug SoC Microarchitecture